1. Field of the Invention
The present invention relates to a DLL (Delay-Locked Loop) circuit used for a polyphase clock generating circuit, a multiply circuit, and the like, particularly to a technique preventing a pseudo lock state which is not normally locked.
2. Related Background Art
The pseudo lock state may be one of the most serious malfunctions of the DLL circuit.
In the conventional technique, as described in U.S. Pat. No. 6,259,290, there is a method in which the pseudo lock state is detected in such a manner that a plurality of pulses are generated within the 1 period of a reference clock by the multiply circuit to count the number of pulses.
However, in the method described in U.S. Pat. No. 6,259,290, such a circuit as the multiply circuit, the counter, and the like is required, and there is a drawback which results in a cost increase and an electrical power consumption increase because the circuit is enlarged.